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| Preliminary Technical Data SUMMARY High performance 32-bit/40-bit floating point processor optimized for high performance automotive audio processing Audio decoder and post processor-algorithm support with 32-bit floating-point implementations Non-volatile memory may be configured to support audio decoders and post processor-algorithms like PCM, Dolby Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ES, MPEG2 AAC, MPEG2 2channel, MP3, and functionalism like Bass management, Delay, Speaker equalization, Graphic equalization, and more. Decoder/post-processor algorithm combination support will vary depending upon the chip version & the system configurations. Please visit www.analog.com/SHARC Single-Instruction Multiple-Data (SIMD) computational architecture SHARC(R) Processor ADSP-21365 On-chip memory--3 Mbits of on-chip SRAM and a dedicated 4 Mbits of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21365 is available in a 300 MHz core instruction rate with unique audio centric peripherals such as the Digital Audio Interface, S/PDIF transceiver, serial ports, DTCP, 8-channel asynchronous sample rate converter, precision clock generators and more. For complete ordering information, see Ordering Guide on page 45 Figure 1. Functional Block Diagram - Processor Core 4 BLOCKS OF ON-CHIP MEMORY CORE PROCESSOR TIMER INSTRUCTION CACHE 32 X 48-BIT BLOCK 0 SRAM 1 MBIT ROM 2 MBIT BLOCK 1 SRAM 1 MBIT BLOCK 2 SRAM 0.5 MBIT BLOCK 3 SRAM 0.5 MBIT ROM 2 MBIT DAG1 8X4X32 DAG2 8X4X32 PROGRAM SEQUENCER ADDR DATA ADDR DATA ADDR DATA ADDR DATA PM ADDRESS BUS DM ADDRESS BUS PM DATA BUS 32 32 64 DM DATA BUS 64 IOA IOD IOA IOD IOA IOD IOA IOD PX REGISTER PROCESSING ELEMENT (PEX) PROCESSING ELEMENT (PEY) IOP REGISTERS (MEMORY MAPPED) 6 JTAG TEST & EMULATION SPI SPORTS IDP PCG TIMERS SRC SPDIF DTCP SIGNAL ROUTING UNIT I/O PROCESSOR AND PERIPHERALS SEE "ADSP-2136x MEMORY AND I/O INTERFACE FEATURES" SECTION FOR DETAILS SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel:781/329-4700 www.analog.com Fax:781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. ADSP-21365 KEY FEATURES - PROCESSOR CORE At 300 MHz (3.33 ns) core instruction rate, the ADSP-21365 performs 1800 MFLOPS/600 MMACS 3 Mbits on-chip dual-ported SRAM (1M Bit block 0, and 1, 0.50M Bit blocks 2 and 3) for simultaneous access by core processor and DMA 4 Mbits on-chip dual-ported mask-programmable ROM (2 Mbits in block 0 and 2 Mbits in block 1) Dual Data Address Generators (DAGs) with modulo and bitreverse addressing Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing Single Instruction Multiple Data (SIMD) architecture provides: Two computational processing elements Concurrent execution Code compatibility with other SHARC family members at the assembly level Parallelism in busses and computational units allows: Single cycle executions (with or without SIMD) of a multiply operation, an ALU operation, a dual memory read or write, and an instruction fetch Transfers between memory and core at a sustained 4.8 Gbytes/s bandwidth at 300 MHz core instruction rate Preliminary Technical Data TDM support for telecommunications interfaces including 128 TDM channel support for newer telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input Data Port provides an additional input path to the DSP core, configurable as 8 channels of serial data or 7 channels of serial data and a single channel of up to a 20-bit wide parallel data Signal Routing Unit provides configurable and flexible connections between all DAI components-six serial ports, one SPI port, eight channels of asynchronous sample rate converters, an S/PDIF receiver/transmitter, three timers, an SPI port,10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins (DAI_Px) Two Serial Peripheral Interfaces (SPI): primary on dedicated pins, secondary on DAI pins Master or slave serial boot through primary SPI Full-duplex operation Master-Slave mode multi-master support Open drain outputs Programmable baud rates, clock polarities and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ADSP-21365 I/O FEATURES DMA Controller supports: 25 zero-overhead DMA channels for transfers between ADSP-21365 internal memory a variety of peripherals 32-bit DMA transfers at core clock speed, in parallel with fullspeed processor execution Asynchronous parallel port provides access to asynchronous external memory 16 multiplexed address/data lines support 24-bit address external address range with 8-bit data or 16-bit address external address range with 16-bit data 50 Mbyte per sec transfer rate 256 word page boundaries External memory access in a dedicated DMA channel 8- to 32- bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital Audio Interface (DAI) includes 6 serial ports, two Precision Clock Generators, an Input Data Port, three timers, an S/PDIF transceiver, DTCP cipher, 8-channel asynchronous sample rate converter, an PI port, and a Signal Routing Unit Six dual data line serial ports that operate at up to 50 Mbits/s on each data line -- each has a clock, frame sync and two data lines that can be configured as either a receiver or transmitter pair Left-justified Sample Pair and I2S Support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port DEDICATED AUDIO COMPONENTS S/PDIF Compatible Digital Audio receiver/transmitter supports: EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards Left justified, I2S or right justified serial data input with 16, 18, 20 or 24 bit word widths (transmitter) Two channel mode and Single Channel Double Frequency (SCDF) mode Sample Rate Converter (SRC) Contains a Serial Input Port, Deemphasis Filter, Sample Rate Converter (SRC) and Serial Output Port providing up to -128db SNR performance Supports Left Justified, I2S, TDM and Right Justified 24, 20, 18 and 16 bit serial formats (input) Digital Transmission Content Protection (DTCP)--a cryptographic protocol for protecting audio content from unauthorized copying, intercepting, and tampering. Pulse Width Modulation provides: 16 PWM outputs configured as four groups of four outputs Supports center-aligned or edge-aligned PWM waveforms Can generate complementary signals on two outputs in paired mode or independent signals in non-paired mode ROM Based Security features include: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multiplier/divider ratios Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA Package Rev. PrA | Page 2 of 46 | December 2003 Preliminary Technical Data GENERAL DESCRIPTION The ADSP-21365 SHARC DSP is a member of the SIMD SHARC family of DSPs that feature Analog Devices' Super Harvard Architecture. The ADSP-21365 is source code compatible with the ADSP-2126x, and ADSP-2116x, DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (Single-Instruction, Single-Data) mode. The ADSP-21365 is a 32bit/40-bit floating point processor optimized for high performance automotive audio applications with its large on-chip SRAM and mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative Digital Audio Interface (DAI). As shown in the functional block diagram on page 1, the ADSP-21365 uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21365 DSP achieves an instruction cycle time of 3.33 ns at 300 MHz. With its SIMD computational hardware, the ADSP-21365 can perform 1800 MFLOPS running at 300 MHz. Table 1 shows performance benchmarks for the ADSP-21365. Table 1. ADSP-21365 Benchmarks (at 300 MHz) Benchmark Algorithm 1024 Point Complex FFT (Radix 4, with reversal) FIR Filter (per tap)1 IIR Filter (per biquad)1 Matrix Multiply (pipelined) [3x3] x [3x1] [4x4] x [4x1] Divide (y/x) Inverse Square Root 1 ADSP-21365 * Three Programmable Interval Timers with PWM Generation, PWM Capture/Pulse width Measurement, and External Event Counter Capabilities * On-Chip SRAM (3 Mbits) * On-Chip mask-programmable ROM (4 Mbits) * 8- or 16-bit Parallel port that supports interfaces to off-chip memory peripherals * JTAG test access port The block diagram of the ADSP-21365 on page 5, illustrates the following architectural features: * DMA controller * Six full duplex serial ports * SPI-compatible interface * Digital Audio Interface that includes a two precision clock generators (PCG), an input data port (IDP), an S/PDIF receiver/transmitter, eight channels asynchronous sample rate converters, DTCP cipher, six serial ports, eight serial interfaces, a 20-bit parallel input port, 10 interrupts, six flag outputs, six flag inputs, three timers, and a flexible signal routing unit (SRU) Figure 2 on page 4 shows one sample configuration of a SPORT using the precision clock generators to interface with an I2S ADC and an I2S DAC with a much lower jitter clock than the serial port would generate itself. Many other SRU configurations are possible. Speed (at 300 MHz) 31 s 1.67 ns 6.66 ns 15 ns 26.60 ns 11.66 ns 18.15 ns ADSP-21365 FAMILY CORE ARCHITECTURE The ADSP-21365 is code compatible at the assembly level with the ADSP-2126x, ADSP-21160 and ADSP-21161, and with the first generation ADSP-2106x SHARC DSPs. The ADSP-21365 shares architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC family of DSPs, as detailed in the following sections. Assumes two files in multichannel SIMD mode The ADSP-21365 continues SHARC's industry leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. These features include 3 Mbits on-chip SRAM memory, 4 Mbits ROM, an I/O processor that supports 25 DMA channels, six serial ports, an SPI interface, external parallel bus, and Digital Audio Interface (DAI). The block diagram of the ADSP-21365 on page 1, illustrates the following architectural features: * Two processing elements, each of which comprises an ALU, Multiplier, Shifter and Data Register File * Data Address Generators (DAG1, DAG2) * Program sequencer with instruction cache * PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle SIMD Computational Engine The ADSP-21365 contains two computational processing elements that operate as a Single-Instruction Multiple-Data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms. Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the band- Rev. PrA | Page 3 of 46 | December 2003 ADSP-21365 ADSP-21365 CLKOUT CLOCK 2 2 3 CLKIN XTAL CLK_CFG1-0 BOOTCFG1-0 FLAG3-1 RD WR FLAG0 ADC (OPTIONAL) CLK FS SDAT ALE AD15-0 LATCH Preliminary Technical Data ADDR DATA OE WE CS PARALLEL PORT RAM ROM BOOT ROM I/O DEVICE CONTROL DATA ADDRESS DAI_P1 DAI _P2 DAI _P3 SRU DAI_P18 DAI_P19 DAI_P20 SCLK0 SFS0 SD0A SD0B SPORT0 SPORT 1 SPORT2 SPORT3 SPORT4 SPO RT5 DAC (OPTIONAL) CLK FS SDAT CLK FS DAI RESET PCGA PCGB JTAG 6 Figure 2. ADSP-21365 System Sample Configuration width between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file. Single-Cycle Fetch of Instruction and Four Operands The ADSP-21365 features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 1 on page 1). With the ADSP-21365's separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier and shifter. These units perform all operations in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multi-function instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats. Instruction Cache The ADSP-21365 includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective -- only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates and FFT butterfly processing. Data Register File A general purpose data register file is contained in each processing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2136x enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0-R15 and in PEY as S0-S15. Rev. PrA | Page 4 of 46 | Data Address Generators With Zero-Overhead Hardware Circular Buffer Support The ADSP-21365's two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital December 2003 Preliminary Technical Data signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the ADSP-21365 contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wrap-around, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. TO PROCESSOR BUSSES AND SYSTEM MEMORY IO DATA BUS (32) IO ADDRESS BUS (18) GPIO FLAGS/IRQ/TIMEXP DMA CONTROLLER 25 CHANNE LS ADSP-21365 4 Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-21365 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching, and fetching up to four 32-bit values from memory--all in a single instruction. 3 CONTROL/G PIO ADDRE SS /DATA BUS/ GP IO 16 PARALLEL PORT PWM (16) 4 ADSP-21365 MEMORY AND I/O INTERFACE FEATURES CONTROL, STATUS, & DATA BUFFERS SPI PORT (1) 4 SPI PORT (1) SIG NAL ROUTING UNIT The ADSP-21365 adds the following architectural features to the SIMD SHARC family core: SERIAL PORTS (6) IOP REGISTERS (MEMORY MAPPED) INPUT DATA PORTS (8) DTCP CIPHER On-Chip Memory The ADSP-21365 contains three megabits of internal SRAM and four megabits of internal mask-programmable ROM. Each block can be configured for different combinations of code and data storage (see Figure 4 on page 6). Each memory block supports single-cycle, independent accesses by the core processor and I/O processor. The ADSP-21365 memory architecture, in combination with its separate on-chip buses, allow two data transfers from the core and one from the I/O processor, in a single cycle. The ADSP-21365's, SRAM can be configured as a maximum of 96K words of 32-bit data, 192K words of 16-bit data, 64K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to three megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one dedicated to each memory block assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. SPDIF (RX/TX) SRC (8 CHANNELS) PRECISION CLOCK GENERATORS (2) 3 TIMERS (3) DIGITAL AUDIO INTERFACE I/O PROCESSOR Figure 3. ADSP-21365 I/O Processor and Peripherals Block Diagram IDP (Input Data Port), the parallel data acquisition port or the parallel port. Twenty-five channels of DMA are available on the ADSP-21365 -- two for the SPI interface, twelve via the serial ports, eight via the Input Data Port two for DTCP and one via the processor's parallel port. Programs can be downloaded to the ADSP-21365 using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers. Digital Audio Interface (DAI) The Digital Audio Interface (DAI) provides the ability to connect various peripherals to any of the DSPs DAI pins (DAI_P[20:1]). Programs make these connections using the Signal Routing Unit (SRU, shown in Figure 3). The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI December 2003 DMA Controller The ADSP-21365's on-chip DMA controller allows data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the ADSP-21365's internal memory and its serial ports, the SPI-compatible (Serial Peripheral Interface) ports, the Rev. PrA | Page 5 of 46 | ADSP-21365 Short Word Addresses Normal Word Addresses Preliminary Technical Data Long Word Addresses Block 3 Block 3 0X001C 0000 - 0X001C 7FFF SRAM 0.5 MBITS 0X000E 0000 - 0X000E 3FFF RAM OR 0X000E 0000 - 0X000E 2AAA 48-BIT ADDRESS 0.5 MBITS Block 3 0X001C 8000 - 0X001F FFFF RESERVED 3.5 MBITS 0X000E 4000 - 0X000F FFFF RESERVED 3.5 MBITS 0X0007 1000 - 0X0007 FFFF RESERVED 3.5 MBITS 0X0007 0000 - 0X0007 1FFF SRAM 0.5 MBIT Block 2 Block 2 Block 2 0X0018 8000 - 0X001B FFFF RESERVED 3.5 MBITS 0X000C 2000 - 0X000D FFFF RESERVED 3.5 MBITS 0X0006 2000 - 0X0006 FFFF RESERVED 3.5 MBITS 0X0018 0000 - 0X0018 7FFF SRAM 0X0017 0000 - 0X0017 FFFF RAM 0X0016 0000 - 0X0016 FFFF RESERVED 0.5 MBITS 0X000C 0000 - 0X000C 3FFF RAM OR 0X000C 0000 - 0X000C 2AAA 48-BIT ADDRESS 0X000B 8000 - 0X000B FFFF RAM OR 0X000B 0000 - 0X000B 5555 48-BIT ADDRESS 0.5 MBITS 0X0006 0000 - 0X0006 1FFF RAM 0.5 MBIT 1 MBIT 1 MBIT 0X0005 C000 - 0X0005 EFFF RAM 1 MBIT Block 1 Block 1 Block 1 1 MBIT 0X000B 0000 - 0X000B 7FFF RESERVED 0X00A 0000 - 0X000A AAAA 48-BIT ADDRESS ROM OR 0X000A 0000 - 0X000A FFFF ROM 0X0009 8000 - 0X0009 FFFF RAM OR 0X0009 0000 - 0X0009 5555 48-BIT ADDRESS RAM 1 MBIT 0X0005 8000 - 0X0005 BFFF RESERVED 1 MBIT 0X0014 0000 - 0X0015 FFFF ROM 2 MBITS 2 MBITS 0X0005 0000 - 0X0005 7FFF ROM 2 MBITS 0X0013 0000 - 0X0013 FFFF RAM 1 MBIT 1 MBIT 0X0004 C000 - 0X0004 FFFF RAM 0X0004 8000 - 0X0004 BFFF RESERVED 1 MBIT Block 0 Block 0 1 MBIT Block 0 0X0012 0000 - 0X0012 FFFF RESERVED 0X0009 0000 - 0X0009 7FFF RESERVED 1 MBIT 1 MBIT 0X0010 0000 - 0X0011 FFFF ROM 2 MBITS 0X008 0000 - 0X0008 FFFF ROM OR 0X0008 0000 - 0X0008 AAAA 48-BIT ADDRESS ROM 0X0000 0000 - 0X003 FFFF IOP REGISTERS 2 MBITS 0X0004 0000 - 0X0004 7FFF ROM 2 MBITS 0X0000 0000 - 0X003 FFFF IOP REGISTERS 0X0000 0000 - 0X003 FFFF IOP REGISTERS Figure 4. ADSP-21365 Memory Map associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths. The DAI also includes six serial ports, a DTCP cipher, an S/PDIF receiver/transmitter, a precision clock generator (PCG), eight channels of asynchronous sample rate converters, an input data port (IDP), an SPI port, six flag outputs and six flag inputs, and 3 timers. The IDP provides an additional input path to the ADSP-21365 core, configurable as either eight channels of I2S serial data or as 7 channels plus a single 20-bit wide synchroRev. PrA | Page 6 of 46 | nous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the ADSP-21365's serial ports. For complete information on using the DAI, see the ADSP2136x SHARC DSP Core Reference. Serial Ports The ADSP-21365 features six synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog devices AD183x December 2003 Preliminary Technical Data family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial ports are enabled via 12 programmable and simultaneous receive or transmit pins that support up to 24 transmit or 24 receive channels of audio data when all six SPORTS are enabled, or six full duplex TDM streams of 128 channels per frame. The serial ports operate at a maximum data rate of 50 Mbits/s. Serial port data can be automatically transferred to and from on-chip memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in four modes: * Standard DSP serial mode * Multichannel (TDM) mode * I S mode * Left-justified sample pair mode Left-justified Sample Pair Mode is a mode in which each Frame Sync cycle two samples of data are transmitted/received -- one sample on the high segment of the frame sync, the other on the low segment of the frame sync. The user has control over various attributes of this mode. Each of the serial ports supports the Left-justified Sample Pair and I2S protocols (I2S is an industry standard interface commonly used by audio codecs, ADCs and DACs such as the Analog Devices AD183x family), with two data pins, allowing four Left-justified Sample Pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 24 I2S channels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the Left-justified Sample Pair and I2S modes, dataword lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional -law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be internally or externally generated. 2 ADSP-21365 Serial Peripheral (Compatible) Interface The ADSP-21365 SHARC processor contains two Serial Peripheral Interface ports (SPI). The SPI is an industry standard synchronous serial link, enabling the ADSP-21365 SPI-compatible port to communicate with other SPI-compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multi-master environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-21365 SPI-compatible peripheral implementation also features programmable baud rate and clock phase and polarities. The ADSP-21365 SPI-compatible port uses open drain drivers to support a multi-master configuration and to avoid data contention. S/PDIF Compatible Digital Audio Receiver/Transmitter and Synchronous/Asynchronous Sample Rate Converter The S/PDIF transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a Biphase encoded signal. The serial data input to the transmitter can be formatted as left justified, I2S or right justified with word widths of 16, 18, 20 or 24 bits. The serial data, clock and frame sync inputs to the S/PDIF transmitter are routed through the Signal Routing Unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCG) or the sample rate converters (SRC) and are controlled by SRU control registers. The sample rate converter (SRC) contains four SRC blocks and is the same core as that used in the AD1896 192 kHz Stereo Asynchronous Sample Rate Converter providing up to 128dB SNR. The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multi-channel audio data without phase mismatches. Finally, the SRC is used to clean up audio data from jittery clock sources such as the S/PDIF receiver. Digital Transmission Content Protection The DTCP specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting and tampering as it traverses high performance digital buses, such as the IEEE 1394 standard. Only legitimate entertainment content delivered to a source device via another approved copy protection system (such as the DVD Content Scrambling System) will be protected by this copy protection system. Parallel Port The Parallel Port provides interfaces to SRAM and peripheral devices. The multiplexed address and data pins (AD15-0) can access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of address. In either mode, 8- or 16bit, the maximum data transfer rate is 50 Mbytes/sec. DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the parallel port register read/write functions. The RD, WR, and ALE (Address Latch Enable) pins are the control pins for the parallel port. Pulse Width Modulation The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor control, electronic valve control or audio power control. The PWM generator can generate either center-aligned or edgealigned PWM waveforms. In addition, it can generate comple- Rev. PrA | Page 7 of 46 | December 2003 ADSP-21365 mentary signals on two outputs in paired mode or independent signals in non-paired mode (applicable to a single group of four PWM waveforms). The entire PWM module has four groups of four PWM outputs each. Therefore this module generates 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM output. The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the mid-point of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. Preliminary Technical Data Phased Locked Loop The ADSP-21365 uses an on-chip Phase Locked Loop (PLL) to generate the internal clock for the core. On power up, the CLKCFG1-0 pins are used to select ratios of 32:1, 16:1, and 6:1. After booting, numerous other ratios can be selected via software control. The ratios are made up of software configurable numerator values from 1 to 64 and software configurable divisor values of 1, 2, 4, and 8. Power Supplies The ADSP-21365 has separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.2V requirement. The external supply must meet the 3.3V requirement. All external supply pins must be connected to the same power supply. Note that the analog supply (AVDD) powers the ADSP-21365's clock generator PLL. To produce a stable clock, you should provide an external circuit to filter the power input to the AVDD pin. Place the filter as close as possible to the pin. For an example circuit, see Figure 5. To prevent noise coupling, use a wide trace for the analog ground (AVSS) signal and install a decoupling capacitor as close as possible to the pin. Note that the AVSS and AVDD pins specified in Figure 5 are inputs to the DSP and not the analog ground plane on the board. Timers The ADSP-21365 has a total of four timers: a core timer able to generate periodic interrupts and three general purpose timers that can that can generate periodic interrupts and be independently set to operate in one of three modes: * Pulse Waveform Generation mode * Pulse Width Count /Capture mode * External Event Watchdog mode The core timer can be configured to use FLAG3 as a Timer Expired signal, and each general purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables all three general purpose timers independently. 10 VDDINT 0.1 F 0.01 F AVDD AVSS ROM Based Security The ADSP-21365 has a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. When using this feature, the DSP does not boot-load any external code, executing exclusively from internal SRAM/ROM. Additionally, the DSP is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or Test Access Port will be assigned to each customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the correct key is scanned. Figure 5. Analog Power (AVDD) Filter Circuit Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21365 processor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor's JTAG interface ensures that the emulator will not affect target system loading or timing. For complete information on Analog Devices' SHARC DSP Tools product line of JTAG emulator operation, see the appropriate "Emulator Hardware User's Guide". Program Booting The internal memory of the ADSP-21365 boots at system power-up from an 8-bit EPROM via the parallel port, an SPI master, an SPI slave or an internal boot. Booting is determined by the Boot Configuration (BOOTCFG1-0) pins. Selection of the boot source is controlled via SPI as either a master or slave device, or it can immediately begin executing from ROM. DEVELOPMENT TOOLS The ADSP-21365 is supported by a complete automotive reference design and development board as well as by a complete home audio reference design board available from Analog Devices. These boards implement complete audio decoding and post processing algorithms that are factory programmed into Rev. PrA | Page 8 of 46 | December 2003 Preliminary Technical Data the ROM of the ADSP-21365. SIMD optimized libraries consume less processing resources, which results in more available processing power for custom proprietary features. The non-volatile memory of the ADSP-21365 can be configured to contain a combination of PCM 96KHz, Dolby Digital, Dolby Prologic, Dolby Prologic II, Dolby Prologic IIx, DTS 96/24, Neo:6, ES, EX, MPEG2 AAC, MPEG2 2channel, MP3, and other functions including bass management, delay, speaker equalization, graphic equalization, and spatialization. Multiple SPDIF and analog I/Os are provided to maximize the overall system flexibility. The ADSP-21365 is supported with a complete set of CROSSCORETM software and hardware development tools, including Analog Devices emulators and VisualDSP++TM development environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-21365. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The SHARC has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer's development schedule, increasing productivity. Statistical profiling enables the programmer to non intrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: * View mixed C/C++ and assembly code (interleaved source and object information) * Insert breakpoints * Set conditional breakpoints on registers, memory, and stacks * Trace instruction execution * Perform linear or statistical profiling of program execution * Fill, dump, and graphically plot the contents of memory * Perform source level debugging * Create custom debugger windows ADSP-21365 The VisualDSP++ IDDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to: * Control how the development tools process inputs and generate outputs * Maintain a one-to-one correspondence with the tool's command line switches The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include Threads, Critical and Unscheduled regions, Semaphores, Events, and Device flags. The VDK also supports Priority-based, Preemptive, Cooperative, and Time-Sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK based objects, and visualizing the system state, when debugging an application that uses the VDK. VisualDSP++ Component Software Engineering (VCSE) is Analog Devices technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. Download components from the Web and drop them into the application. Publish component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language. Use the Expert Linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the DSP or external memory with the drag of the mouse, examine run time stack and heap usage. The Expert Linker is fully compatible with existing Linker Definition File (LDF), allowing the developer to move between the graphical and textual environments. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hardware tools include SHARC processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools. Rev. PrA | Page 9 of 46 | December 2003 ADSP-21365 DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD (TARGET) The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. Nonintrusive incircuit emulation is assured by the use of the processor's JTAG interface--the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the DSP's JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)-- use site search on "EE-68." This document is updated regularly to keep pace with improvements to emulator support. Preliminary Technical Data ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21365 architecture and functionality. For detailed information on the ADSP-2136x Family core architecture and instruction set, refer to the ADSP-2136x DSP Hardware Reference and the ADSP-21160 SHARC DSP Instruction Set Reference. Rev. PrA | Page 10 of 46 | December 2003 Preliminary Technical Data PIN FUNCTION DESCRIPTIONS ADSP-21365 pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Tie or pull unused inputs to VDDEXT or GND, except for the following: ADSP-21365 * DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI and AD15-0 (NOTE: These pins have pull-up resistors.) The following symbols appear in the Type column of Table 2: A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain, and T = Three-State. Table 2. Pin Descriptions Pin AD15-0 Type I/O/T State During & After Reset Three-state with pull-up enabled Function RD O WR O ALE O FLAG3-0 I/O/A Parallel Port Address/Data. The ADSP-21365 parallel port and its corresponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 k internal pull-up resistor. See Address Data Modes on page 14 for details of the AD pin operation: For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 16 external address bits, A23-8; ALE is used in conjunction with an external latch to retain the values of the A23-8. For 16-bit mode: ALE is automatically asserted whenever a change occurs in the address bits, A15-0; ALE is used in conjunction with an external latch to retain the values of the A15-0. To use these pins as flags (FLAGS15-0) or PWMs (PWM15-0): 1) set (=1) bit 20 of the SYSCTL register to disable the parallel port, 2) set (=1) bits 22-25 of the SYSCTL register to enable FLAGS in groups of four (bit 22 for FLAGS30, bit 23 for FLAGS7-4 etc.) or, set (=1) bits 26-29 of the SYSCTL register to enable PWMs in groups of four (bit 26 for PWM0-3, bit 27 for PWM4-7, and so on). When used as an input, the IDP Channel0 can use these pins for parallel input data. Output only, driven Parallel Port Read Enable. RD is asserted low whenever the DSP reads 8-bit or 16high1 bit data from an external memory device. When AD15-0 are flags, this pin remains deasserted. Output only, driven Parallel Port Write Enable. WR is asserted low whenever the DSP writes 8-bit or high1 16-bit data to an external memory device. When AD15-0 are flags, this pin remains deasserted. Output only, driven Parallel Port Address Latch enable. ALE is asserted whenever the DSP drives a low1 new address on the parallel port address pins. On reset, ALE is active high. However, it can be reconfigured using software to be active low. When AD15-0 are flags, this pin remains deasserted. Three-state Flag Pins. Each flag pin is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals. These pins can be used as an SPI interface slave select output during SPI mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals. In SPI master boot mode, FLAG0 is the slave select pin that must be connected to an SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When bit 16 is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0. When bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1. When bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2. When bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP which indicates that the system timer has expired. Rev. PrA | Page 11 of 46 | December 2003 ADSP-21365 Table 2. Pin Descriptions (Continued) Pin DAI_P20-1 Type I/O/T State During & After Reset Three-state with programmable pullup Function Preliminary Technical Data SPICLK I/O Three-state with pull-up enabled SPIDS I Input only MOSI I/O (O/D) Three-state with pull-up enabled MISO I/O (O/D) Three-state with pull-up enabled BOOTCFG1-0 I Input only Digital Audio Interface Pins. These pins provide the physical interface to the SRU. The SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin's output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the SRU may be routed to any of these pins. The SRU provides the connection from the Serial ports, Input data port, precision clock generators and timers, DTCP cipher, S/PDIF transceiver, sample rate converters and SPI to the DAI_P20-1 pins These pins have internal 22.5 k pull-up resistors which are enabled on reset. These pull-ups can be disabled in the DAI_PIN_PULLUP register. Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is transferred. The master may transmit data at a variety of baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word. Slave devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data are programmable into the SPICTL control register and define the transfer format. SPICLK has a 22.5 k internal pull-up resistor. Serial Peripheral Interface Slave Device Select. An active low signal used to select the DSP as an SPI slave device. This input signal behaves like a chip select, and is provided by the master device for the slave devices. In multi-master mode the DSPs SPIDS signal can be driven by a slave device to signal to the DSP (as SPI master) that an error has occurred, as some other device is also trying to be the master device. If asserted low when the device is in master mode, it is considered a multi-master error. For a single-master, multiple-slave configuration where flag pins are used, this pin must be tied or pulled high to VDDEXT on the master device. For ADSP-21365 to ADSP-21365 SPI interaction, any of the master ADSP-21365's flag pins can be used to drive the SPIDS signal on the ADSP-21365 SPI slave device. SPI Master Out Slave In. If the ADSP-21365 is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the ADSP-21365 is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data. In an ADSP-21365 SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 k internal pull-up resistor. SPI Master In Slave Out. If the ADSP-21365 is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the ADSP-21365 is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In an ADSP-21365 SPI interconnection, the data is shifted out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has a 22.5 k internal pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL register. Note: Only one slave is allowed to transmit data at any given time. To enable broadcast transmission to multiple SPI-slaves, the DSP's MISO pin may be disabled by setting (=1) bit 5 (DMISO) of the SPICTL register. Boot Configuration Select. This pin is used to select the boot mode for the DSP. The BOOTCFG pins must be valid before reset is asserted. See Table 3 for a description of the boot modes. Rev. PrA | Page 12 of 46 | December 2003 Preliminary Technical Data Table 2. Pin Descriptions (Continued) Pin CLKIN Type I State During & After Reset Input only Function ADSP-21365 XTAL CLKCFG1-0 O I Output only2 Input only CLKOUT O Output only RESET I/A Input only TCK TMS TDI TDO TRST I I/S I/S O I/A Input only3 Three-state with pull-up enabled Three-state with pull-up enabled Three-state4 Three-state with pull-up enabled Three-state with pull-up enabled EMU O (O/D) VDDINT VDDEXT AVDD P P P AVSS GND 1 2 G G Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21365 clock input. It configures the ADSP-21365 to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21365 to use the external clock source such as an external clock oscillator. The core is clocked either by the PLL output or this clock input depending on the CLKCFG1-0 pin settings. CLKIN may not be halted, changed, or operated below the specified frequency. Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 4 for a description of the clock configuration modes. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. Local Clock Out/ Reset Out. Drives out the core reset signal to an external device. CLKOUT can also be configured as a reset out pin.The functionality can be switched between the PLL output clock and reset out by setting bit 12 of the PMCTREG register. The default is reset out. Processor Reset. Resets the ADSP-21365 to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up. Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21365. Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 k internal pull-up resistor. Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5 k internal pull-up resistor. Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21365. TRST has a 22.5 k internal pull-up resistor. Emulation Status. Must be connected to the ADSP-21365 Analog Devices DSP Tools product line of JTAG emulators target board connector only. EMU has a 22.5 k internal pullup resistor. Core Power Supply. Nominally +1.2 V dc and supplies the DSP's core processor (13 pins on the BGA package, 32 pins on the LQFP package). I/O Power Supply. Nominally +3.3 V dc. (6 pins on the BGA package, 10 pins on the LQFP package). Analog Power Supply. Nominally +1.2 V dc and supplies the DSP's internal PLL (clock generator). This pin has the same specifications as VDDINT, except that added filtering circuitry is required. For more information, see Power Supplies on page 8. Analog Power Supply Return. Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package). RD, WR, and ALE are continuously driven by the DSP and won't be three-stated. Output only is a three-state driver with its output path always enabled. 3 Input only is three-state driver with both output path. 4 Three-state is three-state driver. Rev. PrA | Page 13 of 46 | December 2003 ADSP-21365 BOOT MODES Table 3. Boot Mode Selection BOOTCFG1-0 00 01 10 11 Booting Mode SPI Slave Boot SPI Master Boot Parallel Port boot via EPROM Internal Boot Mode (ROM code only) Preliminary Technical Data CORE INSTRUCTION RATE TO CLKIN RATIO MODES Table 4. Core Instruction Rate/ CLKIN Ratio Selection CLKCFG1-0 00 01 10 Core to CLKIN Ratio 6:1 32:1 16:1 ADDRESS DATA MODES The following table shows the functionality of the AD pins for 8-bit and 16-bit transfers to the parallel port. For 8-bit data transfers, ALE latches address bits A23-A8 when asserted, followed by address bits A7-A0 and data bits D7-D0 when deasserted. For 16-bit data transfers, ALE latches address bits A15-A0 when asserted, followed by data bits D15-D0 when deasserted. Table 5. Address/ Data Mode Selection EP Data Mode 8-bit 8-bit 16-bit 16-bit ALE Asserted Deasserted Asserted Deasserted AD7-0 Function A15-8 D7-0 A7-0 D7-0 AD15-8 Function A23-16 A7-0 A15-8 D15-8 Rev. PrA | Page 14 of 46 | December 2003 Preliminary Technical Data ADSP-21365 SPECIFICATIONS Timing is measured on signals when they cross the 1.5 V level as described in Figure 31 on page 39. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V. ADSP-21365 RECOMMENDED OPERATING CONDITIONS K Grade Parameter1 VDDINT AVDD VDDEXT VIH VIL CLOAD TAMB 1 2 Min Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage2, @ VDDEXT = max Low Level Input Voltage2 @ VDDEXT = min Load Capacitance on Output Pins Ambient Operating Temperature3 0 1.14 1.14 3.13 2.0 -0.5 Max 1.26 1.26 3.47 VDDEXT+0.5 0.8 30 +70 Unit V V V V V pf C Specifications subject to change without notice. Applies to input and bidirectional pins: AD15-0, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKIN, CLKCFGx, RESET, TCK, TMS, TDI, TRST. 3 See Thermal Characteristics on page 40 for information on thermal specifications. ELECTRICAL CHARACTERISTICS Parameter1 VOH VOL IIH IIL IILPU IOZH IOZL IOZLPU IDD-INTYP AIDD CIN 1 2 High Level Output Voltage 2 Low Level Output Voltage2 High Level Input Current4,5 Low Level Input Current4 Low Level Input Current Pull-Up5 Three-State Leakage Current 6,7 Three-State Leakage Current6 Three-State Leakage Current Pull-Up17 Supply Current (Internal)8,9 Supply Current (Analog)10 Input Capacitance11, 12 Test Conditions @ VDDEXT = min, IOH = -1.0 mA3 @ VDDEXT = min, IOL = 1.0 mA3 @ VDDEXT = max, VIN = VDDEXT max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = 0 V @ VDDEXT= max, VIN = VDDEXT max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = 0 V tCCLK = 5.0 ns, VDDINT = 1.2 AVDD = max fIN=1 MHz, TCASE=25C, VIN=1.2V Min 2.4 Max 0.4 10 10 200 10 10 200 500 10 4.7 Unit V V A A A A A A mA mA pF Specifications subject to change without notice. Applies to output and bidirectional pins: AD15-0, RD, WR, ALE, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL. 3 See Output Drive Currents on page 39 for typical drive current capabilities. 4 Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN. 5 Applies to input pins with 22.5 k internal pull-ups: TRST, TMS, TDI. 6 Applies to three-statable pins: FLAG3-0. 7 Applies to three-statable pins with 22.5 k pull-ups: AD15-0, DAI_Px, SPICLK, EMU, MISO, MOSI. 8 Typical internal current data reflects nominal operating conditions. 9 See Engineering-to-Engineering Note (No. TBD) for further information. 10 Characterized, but not tested. 11 Applies to all signal pins. 12 Guaranteed, but not tested. Rev. PrA | Page 15 of 46 | December 2003 ADSP-21365 ABSOLUTE MAXIMUM RATINGS Internal (Core) Supply Voltage (VDDINT)1 Analog (PLL) Supply Voltage (AVDD)1 External (I/O) Supply Voltage (VDDEXT)1 Input Voltage Output Voltage Swing Load Capacitance1 Storage Temperature Range1 1 Preliminary Technical Data 0.3 V to +1.5 V -0.3 V to +1.5 V -0.3 V to +4.6 V -0.5 V to VDDEXT1 + 0.5 V -0.5 V to VDDEXT1 + 0.5 V 200 pF -65C to +150C Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD SENSITIVITY CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21365 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. TIMING SPECIFICATIONS The ADSP-21365's internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP's internal clock frequency and external (CLKIN) clock frequency with the CLKCFG1-0 pins. To determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider control of each port (DIVx for the serial ports). The ADSP-21365's internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the DSP's internal clock (the clock source for the parallel port logic and I/O pads). Note the definitions of various clock periods that are a function of CLKIN and the appropriate ratio control (Table 6). Table 6. ADSP-21365 CLKOUT and CCLK Clock Generation Operation Timing Requirements CLKIN CCLK Timing Requirements tCK tCCLK tPCLK tSCLK tSPICLK 1 Description Input Clock Core Clock Description1 CLKIN Clock Period (Processor) Core Clock Period (Peripheral) Clock Period = 2 x tCCLK Serial Port Clock Period = (tPCLK) x SR SPI Clock Period = (tPCLK) x SPIR Calculation 1/tCK 1/tCCLK where: SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV) SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register) DAI_Px = Serial Port Clock SPICLK = SPI Clock Rev. PrA | Page 16 of 46 | December 2003 Preliminary Technical Data Figure 6 shows Core to CLKIN ratios of 6:1, 16:1 and 32:1 with external oscillator or crystal. ADSP-21365 CLKOUT CLKIN XTAL XTAL OSC PLLILCLK PLL 6:1, 16:1, 32:1 CCLK (CORE CLOCK) CLK-CFG [1:0] Figure 6. Core Clock and System Clock Relationship to CLKIN Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See Figure 31 on page 39 under Test Conditions for voltage reference levels. Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. The ADSP-21365's internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP's internal clock frequency and external (CLKIN) clock frequency with the CLKCFG1-0 pins. To determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider control of each port (DIVx for the serial ports). The ADSP-21365's internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the DSP's internal clock (the clock source for the parallel port logic and I/O pads). Note the following definitions of various clock periods that are a function of CLKIN and the appropriate ratio control. Rev. PrA | Page 17 of 46 | December 2003 ADSP-21365 Power up Sequencing The timing requirements for DSP startup are given in Table 7. Table 7. Power Up Sequencing Timing Requirements (DSP Startup) Name Parameter Timing Requirements tRSTVDD RESET low before VDDINT/VDDEXT on tIVDDEVDD VDDINT on before VDDEXT CLKIN valid after VDDINT/VDDEXT valid1 tCLKVDD tCLKRST CLKIN valid before RESET deasserted tPLLRST PLL control setup before RESET deasserted tWRST Subsequent RESET low pulse width4 Switching Characteristics tCORERST DSP core reset deasserted after RESET deasserted 1 Preliminary Technical Data Min 0 -50 0 102 203 4tCK 4096tCK + 2 tCCLK 4, 5 Max Units ns ms ms s s ns 200 200 Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem. 2 Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time. Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal. 3 Based on CLKIN cycles 4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and propagate default states at all I/O pins. 5 The 4096 cycle count depends on tSRST specification in Table 9. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum. RESET tRSTVDD VDDINT tIVDDEVDD VDDEXT tCLKVDD CLKIN tCLKRST CLK_CFG1-0 tPLLRST RSTOUT tCORERST Figure 7. Power Up Sequencing Rev. PrA | Page 18 of 46 | December 2003 Preliminary Technical Data Clock Input Table 8. Clock Input Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4V-2.0V) tCCLK CCLK Period3 1 2 ADSP-21365 300 MHz Min 19.81 81 81 3.31 Units Max TBD2 TBD2 TBD2 TBD TBD ns ns ns ns ns Applies only for CLKCFG1-0 = 00 and default values for PLL control bits in PMCTL. Applies only for CLKCFG1-0 = 01 and default values for PLL control bits in PMCTL. 3 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK. tCK CLKIN tCKH tCKL Figure 8. Clock Input Clock Signals The ADSP-21365 can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-21365 to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 9 shows the component connections used for a crystal operating in fundamental mode. CLKIN 1M XTAL C1 X1 C2 NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01. Figure 9. 300 MHz Operation (Fundamental Mode Crystal) Rev. PrA | Page 19 of 46 | December 2003 ADSP-21365 Reset Table 9. Reset Parameter Timing Requirements tWRST RESET Pulse Width Low1 tSRST RESET Setup Before CLKIN Low 1 Preliminary Technical Data Min 4tCK 8 Max Units ns ns Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). CLKIN tWRST RESET tSRST Figure 10. Reset Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts. Table 10. Interrupts Parameter Timing Requirements tIPW IRQx Pulse Width Min 2 x tPCLK +2 Max Units ns FLAG2-0 (IRQ2-0) tIPW Figure 11. Interrupts Rev. PrA | Page 20 of 46 | December 2003 Preliminary Technical Data Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (CTIMER). Table 11. Core Timer Parameter Switching Characteristic tWCTIM CTIMER Pulse width Min 4 x tPCLK - 1 Max ADSP-21365 Units ns FLAG3 (CTIMER) tWCTIM Figure 12. Core Timer Timer PWM_OUT Cycle Timing The following timing specification applies to Timer[2:0] in PWM_OUT (pulse width modulation) mode. Timer signals are routed to the DAI_P[20:1] pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P[20:1] pins. Table 12. Timer[2:0] PWM_OUT Timing Parameter Switching Characteristic tPWMO Timer[2:0] Pulse width Output Min 2 tPCLK - 1 Max 2(231 - 1) tPCLK Units ns tPWMO DAI_P[20:1] (TIMER[2:0]) Figure 13. Timer[2:0] PWM_OUT Timing Rev. PrA | Page 21 of 46 | December 2003 ADSP-21365 Timer WDTH_CAP Timing The following timing specification applies to Timer[2:0] in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P[20:1] pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P[20:1] pins. Table 13. Timer[2:0] Width Capture Timing Parameter Timing Requirement tPWI Timer[2:0] Pulse width Min 2 tPCLK Max Preliminary Technical Data Units ns 2(231-1) tPCLK tPWI DAI_P[20:1] (TIMER[2:0]) Figure 14. Timer[2:0] Width Capture Timing DAI Pin to Pin Direct Routing For direct pin connections only (for example DAI_PB01_I to DAI_PB02_O). Table 14. DAI Pin to Pin Routing Parameter Timing Requirement tDPIO Delay DAI Pin Input Valid to DAI Output Valid Min 1.5 Max 10 Units ns DAI_Pn DAI_Pm tDPIO Figure 15. DAI Pin to PIN Direct Routing Rev. PrA | Page 22 of 46 | December 2003 Preliminary Technical Data Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the Precision Clock Generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG's Table 15. Precision Clock Generator (Direct Pin Routing) Parameter Timing Requirement tPCGIW Input Clock Period tSTRIG PCG Trigger Setup Before Falling Edge of PCG Input Clock PCG Trigger Hold After Falling Edge of PCG Input Clock tHTRIG Switching Characteristics tDPCGIO PCG Output Clock and Frame Sync Active Edge Delay After PCG Input Clock tDTRIG PCG Output Clock and Frame Sync Delay After PCG Trigger tPCGOW Output Clock Period Min 20 2 2 Max ADSP-21365 inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is not timing data available. All Timing Parameters and Switching Characteristics apply to external DAI pins (DAI_P07 - DAI_P20). Units ns ns 2.5 2.5 + 2.5 x tPCGOW 40 10 ns 10 + 2.5 x tPCGOW ns tSTRIG DAI_Pn PCG_TRIGx_I tHTRIG DAI_Pm PCG_EXTx_I (CLKIN) DAI_Py PCG_CLKx_O tDPCGIO tPCGIW tPCGOW DAI_Pz PCG_FSx_O tDTRIG Figure 16. Precision Clock Generator (Direct Pin Routing) Rev. PrA | Page 23 of 46 | December 2003 ADSP-21365 Flags The timing specifications provided below apply to the FLAG[3:0] and DAI_P[20:1] pins, the parallel port and the serial peripheral interface (SPI). See Table 2, "Pin Descriptions," on page 11 for more information on flag use. Table 16. Flags Parameter Timing Requirement tFIPW FLAG[3:0] IN Pulse Width Switching Characteristic FLAG[3:0] OUT Pulse Width tFOPW Min Preliminary Technical Data Max Units ns ns 2 x tPCLK+3 2 x tPCLK - 1 DAI_P[20:1] (FLAG3-0IN) (AD[15:0] tFIPW DAI_P[20:1] (FLAG3-0OUT) (AD[15:0] tFOPW Figure 17. Flags Rev. PrA | Page 24 of 46 | December 2003 Preliminary Technical Data Memory Read-Parallel Port Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21365 is accessing external memory space. Table 17. 8-Bit Memory Read Cycle Parameter Timing Requirements Address/data [7:0] setup before RD high tDRS tDRH Address/data [7:0] hold after RD high tDAD Address [15:8] to data valid Switching Characteristics tALEW ALE pulse width tADAS Address/data [15:0] setup before ALE deasserted1 Address/data [15:0] hold after ALE deasserted1 tADAH tALEHZ ALE deasserted1 to Address/Data[7:0] in high Z tRW RD pulse width tADRH Address/data [15:8] hold after RD high D = (Data Cycle Duration) x tPCLK H= tPCLK (if a hold cycle is specified, else H = 0) 1 ADSP-21365 Min 3.3 0 Max Units ns ns ns ns ns D + tPCLK - 3.5 2 x tPCLK - 2.0 2 x tPCLK - 1.0 tPCLK - 0.8 tPCLK - 0.8 D-2 H tPCLK ns ns ns On reset, ALE is an active high cycle. However, it can be configured by software to be active low ALE tALEW RD tRW WR tALEHZ tADAS tADAH tADRH AD[15:8] VALID ADDRESS VALID ADDRESS tDRS tDRH AD[7:0] VALID ADDRESS tDAD VALID DATA Figure 18. Read Cycle For 8-bit Memory Timing Rev. PrA | Page 25 of 46 | December 2003 ADSP-21365 Table 18. 16-bit Memory Read Cycle Parameter Timing Requirements tDRS Address/data [15:0] setup before RD high Address/data [15:0] hold after RD high tDRH Switching Characteristics tALEW ALE pulse width tADAS Address/data [15:0] setup before ALE deasserted1 tADAH Address/data [15:0] hold after ALE deasserted1 tALEHZ ALE deasserted1 to Address/Data[15:0] in high Z tRW RD pulse width D = (Data Cycle Duration) x tPCLK H = tPCLK (if a hold cycle is specified, else H = 0) 1 Preliminary Technical Data Min 3.3 0 2 x tPCLK - 2 2 x tPCLK - 1.0 tPCLK - 0.8 tPCLK - 0.8 D-2 Max Units ns ns ns ns ns ns ns ns On reset, ALE is an active high cycle. However, it can be configured by software to be active low. ALE tALEW RD tRW WR tADAS AD[15:0] VALID ADDRESS tADAH tDRS tDRH VALID DATA tALEHZ Figure 19. Read Cycle For 16-bit Memory Timing Rev. PrA | Page 26 of 46 | December 2003 Preliminary Technical Data Memory Write--Parallel Port Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21365 is accessing external memory space. Table 19. 8-bit Memory Write Cycle Parameter Switching Characteristics: ALE pulse width tALEW tADAS Address/data [15:0] setup before ALE deasserted1 tALERW ALE Deasserted to Read/Write Asserted tADAH Address/data [15:0] hold after ALE deasserted 1 tWW WR pulse width tADWL Address/data [15:8] to WR low Address/data [15:8] hold after WR high tADWH tALEHZ ALE deasserted1 to Address/Data[15:0] in high Z tDWS Address/data [7:0] setup before WR high tDWH Address/data [7:0] hold after WR high tDAWH Address/data to WR high D = (Data Cycle Duration) x tPCLK H = tPCLK (if a hold cycle is specified, else H = 0) 1 ADSP-21365 Min 2 x tPCLK - 2 2 x tPCLK - 1.0 1 x tCCLK - 1 tPCLK - 0.5 D-2 tPCLK - 1.5 H tPCLK - 1.5 D H D Max Units ns ns ns ns ns ns ns ns ns ns ns On reset, ALE is an active high cycle. However, it can be configured by software to be active low ALE tALEW tDAWH WR tWW RD tALEHZ tADAS tADAH tADWL tADWH AD[15:8] VALID ADDRESS VALID ADDRESS tDWS tDWH AD[7:0] VALID ADDRESS VALID DATA Figure 20. Write Cycle For 8-bit Memory Timing Rev. PrA | Page 27 of 46 | December 2003 ADSP-21365 Preliminary Technical Data Table 20. 16-bit Memory Write Cycle Parameter Switching Characteristics tALEW ALE pulse width tADAS Address/data [15:0] setup before ALE deasserted1 tADAH Address/data [15:0] hold after ALE deasserted1 tWW WR pulse width ALE deasserted1 to Address/Data[15:0] in high Z tALEHZ tDWS Address/data [15:0] setup before WR high tDWH Address/data [15:0] hold after WR high D = (Data Cycle Duration) x tPCLK H = tPCLK (if a hold cycle is specified, else H = 0) 1 Min 2 x tPCLK - 2 2 x tPCLK - 1.0 tPCLK - 0.5 D-2 tPCLK - 1.5 D H Max Units ns ns ns ns ns ns ns On reset, ALE is an active high cycle. However, it can be configured by software to be active low. ALE tALEW WR tWW RD tALEHZ tADAS tADAH tDWS tDWH AD[15:0] VALID ADDRESS VALID DATA Figure 21. Write Cycle For 16-bit Memory Timing Rev. PrA | Page 28 of 46 | December 2003 Preliminary Technical Data Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 21. Serial Ports--External Clock Parameter Timing Requirements tSFSE FS Setup Before SCLK (Externally Generated FS in either Transmit or Receive Mode)1 tHFSE FS Hold After SCLK (Externally Generated FS in either Transmit or Receive Mode)1 tSDRE Receive Data Setup Before Receive SCLK1 tHDRE Receive Data Hold After SCLK1 tSCLKW SCLK Width tSCLK SCLK Period Switching Characteristics tDFSE FS Delay After SCLK (Internally Generated FS in either Transmit or Receive Mode) 2 FS Hold After SCLK tHOFSE (Internally Generated FS in either Transmit or Receive Mode)1 tDDTE Transmit Data Delay After Transmit SCLK1 Transmit Data Hold After Transmit SCLK1 tHDTE 1 ADSP-21365 Serial port signals (SCLK, FS, DxA,/DxB) are routed to the DAI_P[20:1] pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P[20:1] pins. Min Max Units 4 5.5 4 5.5 20 40 ns ns ns ns ns ns 7 2 7 2 ns ns ns ns Referenced to sample edge. 2 Referenced to drive edge. Table 22. Serial Ports--Internal Clock Parameter Timing Requirements tSFSI FS Setup Before SCLK (Externally Generated FS in either Transmit or Receive Mode)1 tHFSI FS Hold After SCLK (Externally Generated FS in either Transmit or Receive Mode)1 Receive Data Setup Before SCLK1 tSDRI tHDRI Receive Data Hold After SCLK1 Switching Characteristics tDFSI FS Delay After SCLK (Internally Generated FS in Transmit Mode)2 tHOFSI FS Hold After SCLK (Internally Generated FS in Transmit Mode)1 tDFSI FS Delay After SCLK (Internally Generated FS in Receive or Mode) FS Hold After SCLK tHOFSI (Internally Generated FS in Receive Mode) tDDTI Transmit Data Delay After SCLK1 tHDTI Transmit Data Hold After SCLK1 Transmit or Receive SCLK Width tSCLKIW 1 Min Max Units 7 -4 7 2.5 ns ns ns ns 3 -1.5 3 -4 3 -1.5 0.5tSCLK-2 0.5tSCLK+2 ns ns ns ns ns ns ns Referenced to the sample edge. 2 Referenced to drive edge. Rev. PrA | Page 29 of 46 | December 2003 ADSP-21365 Table 23. Serial Ports--Enable and Three-State Parameter Switching Characteristics tDDTEN Data Enable from External Transmit SCLK1 Data Disable from External Transmit SCLK1 tDDTTE tDDTIN Data Enable from Internal Transmit SCLK1 1 Preliminary Technical Data Min 2 7 0 Max Units ns ns ns Referenced to drive edge. Table 24. Serial Ports--External Late Frame Sync Parameter Min Switching Characteristics tDDTLFSE Data Delay from Late External Transmit FS or External Receive FS with MCE = 1, MFD = 01 tDDTENFS Data Enable for MCE = 1, MFD = 01 0.5 1 Max Units 7 ns ns The tDDTLFSE and tDDTENFS parameters apply to Left-justified Sample Pair as well as DSP serial mode, and MCE = 1, MFD = 0. EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DIA_P[20:0] (SCLK) DRIVE SAMPLE tHFSE/I tSFSE/I DIA_P[20:0] (FS) tDDTENFS DIA_P[20:0] (DXA/DXB) tDDTLFSE tHDTE/I 1ST BIT 2ND BIT tDDTE/I DRIVE LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE tHFSE/I DRIVE DIA_P[20:0] (SCLK) tSFSE/I DIA_P[20:0] (FS) tDDTENFS DIA_P[20:0] (DXA/DXB) tDDTLFSE tHDTE/I 1ST BIT tDDTE/I 2ND BIT NOTE SERIAL PORT SIGNALS (SCLK, FS, DXA,/DXB) ARE ROUTED TO THE DAI_P[20:1] PINS USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS. Figure 22. External Late Frame Sync1 1 This figure reflects changes made to support Left-justified Sample Pair mode. Rev. PrA | Page 30 of 46 | December 2003 Preliminary Technical Data ADSP-21365 DATA RECEIVE-- INTERNAL CLOCK DRIVE EDGE tSCLKIW DAI_P[20:1] (SCLK) tDFSI tHOFSI DAI_P[20:1] (FS) tSDRI DAI_P[20:1] (DXA/DXB) tHDRI DAI_P[20:1] (DXA/DXB) tSFSI tHFSI DAI_P[20:1] (FS) DAI_P[20:1] (SCLK) SAMPLE EDGE DATA RECEIVE-- EXTERNAL CLOCK DRIVE EDGE tSCLKW SAMPLE EDGE tDFSE tHOFSE tSFSE tHFSE tSDRE tHDRE NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT -- INTERNAL CLOCK DRIVE EDGE tSCLKIW DAI_P[20:1] (SCLK) tDFSI tHOFSI DAI_P[20:1] (FS) tHDTI DAI_P[20:1] (DXA/DXB) tDDTI DAI_P[20:1] (DXA/DXB) tSFSI tHFSI DAI_P[20:1] (FS) DAI_P[20:1] (SCLK) SAMPLE EDGE DATA TRANSMIT -- EXTERNAL CLOCK DRIVE EDGE tSCLKW SAMPLE EDGE tDFSE tHOFSE tSFSE tHFSE tHDTE tDDTE NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DRIVE EDGE DAI_P[20:1] SCLK (EXT) SCLK tDDTEN tDDTTE DRIVE EDGE DAI_P[20:1] D XA/DXB DRIVE EDGE DAI_P[20:1] SCLK (INT) SCLK tDDTIN tDDTTI DRIVE EDGE DAI_P[20:1] D XA/DXB Figure 23. Serial Ports Rev. PrA | Page 31 of 46 | December 2003 ADSP-21365 Input Data Port The timing requirements for the IDP are given in Table 25.IDP Signals (SCLK, FS, SDATA) are routed to the DAI_P[20:1] pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P[20:1] pins. Table 25. IDP Parameter Timing Requirements tSIFS FS Setup Before SCLK Rising Edge1 tSIHFS FS Hold After SCLK Rising Edge1 SData Setup Before SCLK Rising Edge1 tSISD tSIHD SData Hold After SCLK Rising Edge1 tIDPCLKW Clock Width tIDPCLK Clock Period 1 Preliminary Technical Data Min 4 5.5 4 5.5 9 20 Max Units ns ns ns ns ns ns DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSISCLKW DAI_P[20:1] (SCLK) tSIHFS tSISFS DAI_P[20:1] (FS) tSISD DAI_P[20:1] (SDATA) tSIHD Figure 24. IDP Master Timing Rev. PrA | Page 32 of 46 | December 2003 Preliminary Technical Data Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 26. PDAP is the parallel mode operation of channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2136x Peripherals Manual. Note that the Table 26. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements tSPCLKEN PDAP_CLKEN Setup Before PDAP_CLK Sample Edge1 tHPCLKEN PDAP_CLKEN Hold After PDAP_CLK Sample Edge1 PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge1 tPDSD tPDHD PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge1 tPDCLKW Clock Width tPDCLK Clock Period tPDHLDD Delay of PDAP strobe after last PDAP_CLK capture edge for a word tPDSTRB 1 ADSP-21365 most significant 16 bits of external PDAP data can be provided through either the parallel port AD[15:0] or the DAI_P[20:5] pins. The remaining 4 bits can only be sourced through DAI_P[4:1]. The timing below is valid at the DAI_P[20:1] pins or at the AD[15:0] pins. Min 4 5.5 4 5.5 9 20 2 x tPCLK 2 x tPCLK Max Units ns ns ns ns ns ns ns ns PDAP Strobe Pulse Width Source pins of DATA are ADDR[7:0], DATA[7:0], or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG. SAMPLE EDGE tPDCLKW DAI_P[20:1] (PDAP_CLK) tSPHLD DAI_P[20:1] (PDAP_CLKEN) tPDSD DATA tPDHD tHPHLD DAI_P[20:1] (PDAP_STROBE) tPDSTRB tPDHLDD Figure 25. PDAP Timing Rev. PrA | Page 33 of 46 | December 2003 ADSP-21365 Sample Rate Converter TBD Preliminary Technical Data S/PDIF Compatible Transiever TBD Rev. PrA | Page 34 of 46 | December 2003 Preliminary Technical Data SPI Interface--Master Table 27. SPI Interface Protocol -- Master Switching and Timing Specifications Parameter Switching Characteristics tSPICLKM Serial clock cycle tSPICHM Serial clock high period tSPICLM Serial clock low period tDDSPIDM SPICLK edge to data out valid (data out delay time) tHDSPIDM SPICLK edge to data out not valid (data out hold time) tSDSCIM FLAG3-0IN (SPI device select) low to first SPICLK edge tHDSM Last SPICLK edge to FLAG3-0IN high tSPITDM Sequential transfer delay Timing Requirements tSSPIDM Data input valid to SPICLK edge (data input set-up time) SPICLK last sampling edge to data input not valid tHSPIDM Min 8 x tPCLK 4 x tPCLK 4 x tPCLK - 2 0 2 4 x tPCLK - 2 4 x tPCLK - 1 4 x tPCLK - 1 Max ADSP-21365 Units ns ns ns ns ns ns ns 8 2 ns ns FLAG3-0 (OUTPUT) tSDSCIM SPICLK (CP = 0) (OUTPUT) tSPICHM tSPICLM tSPICLKM tHDSM t S P I TD M tSPICLM SPICLK (CP = 1) (OUTPUT) tSPICHM tDDSPIDM MOSI (OUTPUT) MSB t HDSPIDM LSB tSSPIDM CPHASE=1 MISO (INPUT) MSB VALID t S S P ID M tHSSPIDM LSB VALID tHSPIDM tDDSPIDM MOSI (OUTPUT) CPHASE=0 MISO (INPUT) MSB tHDSPIDM LSB t S S P ID M MSB VALID tHSPIDM LSB VALID Figure 26. SPI Master Timing Rev. PrA | Page 35 of 46 | December 2003 ADSP-21365 SPI Interface--Slave Table 28. SPI Interface Protocol --Slave Switching and Timing Specifications Parameter Switching Characteristics tDSOE SPIDS assertion to data out active tDSDHI SPIDS deassertion to data high impedance tDDSPIDS SPICLK edge to data out valid (data out delay time) tHDSPIDS SPICLK edge to data out not valid (data out hold time) tDSOV SPIDS assertion to data out valid (CPHASE=0) Timing Requirements Serial clock cycle tSPICLKS tSPICHS Serial clock high period tSPICLS Serial clock low period tSDSCO SPIDS assertion to first SPICLK edge CPHASE = 0 CPHASE = 1 tHDS Last SPICLK edge to SPIDS not asserted CPHASE = 0 tSSPIDS Data input valid to SPICLK edge (data input set-up time) tHSPIDS SPICLK last sampling edge to data input not valid tSDPPW SPIDS deassertion pulse width (CPHASE=0) Min 0 0 Preliminary Technical Data Max 4 4 9.4 5 x tPCLK Units ns ns ns ns ns ns ns ns ns 2 x tPCLK 4 x tPCLK 2 x tPCLK 2 x tPCLK - 2 2 x tPCLK 2 x tPCLK 2 x tPCLK ns 2 2 2 x tPCLK ns ns ns Rev. PrA | Page 36 of 46 | December 2003 Preliminary Technical Data ADSP-21365 SPIDS (INPUT) t S P IC H S SPICLK (CP = 0) (INPUT) tSPICLS tSPICLKS tHDS tSDPPW tSDSCO SPICLK (CP = 1) (INPUT) tSPICLS tSPICHS tDSOE tDDSPIDS tDDSPIDS MSB LSB tDSDHI t H D LS B S MISO (OUTPUT) CPHASE=1 MOSI (INPUT) tHSPIDS tSSPIDS MSB VALID tSSPIDS LSB VALID tDSOV tD S O E MISO (OUTPUT) CPHASE=0 MOSI (INPUT) MSB tDDSPIDS tHDLSBS tDSDHI LSB tSSPIDS MSB VALID LSB VALID tHSPIDS Figure 27. SPI Slave Timing Rev. PrA | Page 37 of 46 | December 2003 ADSP-21365 JTAG Test Access Port and Emulation Table 29. JTAG Test Access Port and Emulation Parameter Timing Requirements tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High tHTAP TDI, TMS Hold After TCK High tSSYS System Inputs Setup Before TCK Low1 tHSYS System Inputs Hold After TCK Low1 tTRSTW TRST Pulse Width Switching Characteristics tDTDO TDO Delay from TCK Low tDSYS System Outputs Delay After TCK Low2 1 2 Preliminary Technical Data Min tCK 5 6 7 18 4tCK Max Units ns ns ns ns ns ns 13 30 ns ns System Inputs = AD15-0, SPIDS, CLKCFG1-0, RESET, BOOTCFG1-0, MISO, MOSI, SPICLK, DAI_Px, FLAG3-0. System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15-0, RD, WR, FLAG3-0, CLKOUT, EMU, ALE. tTCK TCK tSTAP TMS TDI tDTDO TDO tSSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS tHSYS tHTAP Figure 28. IEEE 11499.1 JTAG Test Access Port Rev. PrA | Page 38 of 46 | December 2003 Preliminary Technical Data OUTPUT DRIVE CURRENTS Figure 29 shows typical I-V characteristics for the output drivers of the ADSP-21365. The curves represent the current drive capability of the output drivers as a function of output voltage. ADSP-21365 CAPACITIVE LOADING Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 30). Figure 34 shows graphically how output delays and holds vary with load capacitance. The graphs of Figure 32, Figure 34 and Figure 33 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20%-80%, V=Min) vs. Load Capacitance. 120 100 LOAD (VDDEXT) CURRENT - mA 80 60 40 20 0 VOH 3.47V, TBD 3.3V, TBD 3.13V, TBD 16.0 14.0 RISE AND FALL TIMES - NS (.694V - 2.77V, 20% - 80%) -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 2 2.5 SOURCE (VDDEXT) VOLTAGE - V 3 3.5 3.47V, TBD 3.3V, TBD 3.13V, TBD VOL 12.0 10.0 8.0 6.0 4.0 2.0 Figure 29. ADSP-21365 Typical Drive 0 0 20 40 60 80 100 120 140 160 180 200 TEST CONDITIONS The ac signal specifications (timing parameters) appear Table 9 on page 20 through Table 29 on page 38. These include output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage reference levels in Figure 30. LOAD CAPACITANCE - PF Figure 32. Typical Output Rise/Fall Time (20%-80%, VDDEXT = Max) 16.0 50 1.5V 14.0 RISE AND FALL TIMES - ns (0.694v - 2.77v, 20% - 80%) TO OUTPUT PIN 30pF 12.0 10.0 8.0 6.0 4.0 2.0 0 0 20 40 60 80 100 120 140 160 180 200 Figure 30. Equivalent Device Loading for AC Measurements (Includes All Fixtures) INPUT 1.5V OR OUTPUT LOAD CAPACITANCE - pF 1.5V Figure 33. Typical Output Fall Time (20%-80%, VDDEXT = Min) Figure 31. Voltage Reference Levels for AC Measurements Rev. PrA | Page 39 of 46 | December 2003 ADSP-21365 Where: Preliminary Technical Data TA = Ambient Temperature 0C OUTPUT DELAY OR HOLD - ns 25 Values of JC are provided for package comparison and PCB design considerations when an external heatsink is required. Values of JB are provided for package comparison and PCB design considerations. Table 30. Thermal Characteristics for 136 Ball BGA1 Parameter JA JMA JMA JB JC JT JMT JMT 1 20 15 10 5 NOMINAL -5 0 30 60 90 120 150 LOAD CAPACITANCE - pF 180 210 Figure 34. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s - - Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical TBD TBD TBD TBD TBD TBD TBD TBD Units C/W C/W C/W C/W C/W C/W C/W C/W The thermal characteristics values provided in this table are modeled values. ENVIRONMENTAL CONDITIONS The ADSP-21365 is available in 136-Ball Grid Array (BGA) package. THERMAL CHARACTERISTICS The ADSP-21365 processor is rated for performance over the commercial temperature range, TAMB = 0C to 70C. Table 30 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to-board measurement complies with JESD51-8. The junction-to-case measurement complies with MIL- STD-883. All measurements use a 2S2P JEDEC test board. To determine the Junction Temperature of the device while on the application PCB, use: T J = T CASE + ( JT x PD ) Where: TJ= Junction temperature 0C TCASE= Case temperature (0C) measured at the top center of the package JT= Junction-to-Top (of package) characterization parameter = Typical value from the tables below PD= Power dissipation see EE Note #TBD Values of JA are provided for package comparison and PCB design considerations. JA can be used for a 1st order approximation of TJ by the equation: T J = T A + ( JA x PD ) Rev. PrA | Page 40 of 46 | December 2003 Preliminary Technical Data 136-BALL BGA PIN CONFIGURATIONS Table 31. 136-Ball BGA Pin Assignments Pin Name CLKCFG0 XTAL TMS TCK TDI CLKOUT TDO EMU MOSI MISO SPIDS VDDINT GND GND VDDINT GND GND GND GND GND GND GND GND FLAG3 BGA Pin# A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 E01 E02 E04 E05 E06 E09 E10 E11 E13 E14 Pin Name CLKCFG1 GND VDDEXT CLKIN TRST AVSS AVDD VDDEXT SPICLK RESET VDDINT GND GND GND FLAG1 FLAG0 GND GND GND GND GND GND FLAG2 DAI_P20 (SFS45) BGA Pin# B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 F01 F02 F04 F05 F06 F09 F10 F11 F13 F14 Pin Name BOOTCFG1 BOOTCFG0 GND GND GND VDDINT BGA Pin# C01 C02 C03 C12 C13 C14 Pin Name VDDINT GND GND GND GND GND GND GND GND VDDINT ADSP-21365 BGA Pin# D01 D02 D04 D05 D06 D09 D10 D11 D13 D14 AD7 VDDINT VDDEXT DAI_P19 (SCLK45) G01 G02 G13 G14 AD6 VDDEXT DAI_P18 (SD5B) DAI_P17 (SD5A) H01 H02 H13 H14 Rev. PrA | Page 41 of 46 | December 2003 ADSP-21365 Table 31. 136-Ball BGA Pin Assignments (Continued) Pin Name AD5 AD4 GND GND GND GND GND GND VDDINT DAI_P16 (SD4B) AD15 ALE RD VDDINT VDDEXT AD8 VDDINT DAI_P2 (SD0B) VDDEXT DAI_P4 (SFS0) VDDINT VDDINT GND DAI_P10 (SD2B) BGA Pin# J01 J02 J04 J05 J06 J09 J10 J11 J13 J14 N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 Pin Name AD3 VDDINT GND GND GND GND GND GND GND DAI_P15 (SD4A) AD14 AD13 AD12 AD11 AD10 AD9 DAI_P1 (SD0A) DAI_P3 (SCLK0) DAI_P5 (SD1A) DAI_P6 (SD1B) DAI_P7 (SCLK1) DAI_P8 (SFS1) DAI_P9 (SD2A) DAI_P11 (SD3A) BGA Pin# K01 K02 K04 K05 K06 K09 K10 K11 K13 K14 P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 Pin Name AD2 AD1 GND GND GND GND GND GND GND DAI_P14 (SFS23) Preliminary Technical Data BGA Pin# L01 L02 L04 L05 L06 L09 L10 L11 L13 L14 Pin Name AD0 WR GND GND DAI_P12 (SD3B) DAI_P13 (SCLK23) BGA Pin# M01 M02 M03 M12 M13 M14 Rev. PrA | Page 42 of 46 | December 2003 Preliminary Technical Data 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P ADSP-21365 KEY VDDINT VDDEXT GND* AVSS AVDD I/O SIGNALS *USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD'S GROUND PLANE. Figure 35. 136-Ball BGA Pin Assignments (Bottom View, Summary) Rev. PrA | Page 43 of 46 | December 2003 ADSP-21365 PACKAGE DIMENSIONS The ADSP-21365 is available in a 136-ball BGA package. All dimensions are in millimeters (mm). Figure 36. 136-ball BGA () Preliminary Technical Data 12.00 SQ BSC A1 BALL PAD CORNER 0.80 TYP A B C D E F G H J K L M N P 10.40 BSC A1 BALL PAD CORNER Top View 12.00 SQ BSC 10.40 BSC 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DETAIL A 1.70 MAX 0.80 TYP DETAIL A 0.85 MIN 0.25 MIN 0.55 0.50 0.45 BALL DIAMETER 0.12 MAX SEATING PLANE ALL DIMENSIONS IN MILIMETERS (MM). 1. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.150 MM OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.08 MM OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID. 2. COMPLIANT TO JEDEC REGISTERED OUTLINE MO-205-AE WITH THE EXCEPTION OF DIMENSION "b" Rev. PrA | Page 44 of 46 | December 2003 Preliminary Technical Data ORDERING GUIDE Analog Devices offers a wide variety of audio algorithms and combinations to run on the ADSP-21365 DSP. These products are sold as part of a chip set, bundled with necessary application software under special part numbers. For a complete list, visit our web site at www.analog.com\SHARC. Part Number1,2,3 ADSP-21365SKBCZENG ADSP-21365SKBC-ENG 1 2 ADSP-21365 These product also may contain 3rd party IPs that may require users to have authorization from the respective IP holders to receive them. Royalty for use of the 3rd party IPs may also be payable by users. Ambient Temperature Range 0C to +70C 0C to +70C Instruction Rate 300 MHz 300 MHz On-Chip SRAM 3 Mbit 3 Mbit ROM 4 Mbit 4 Mbit Operating Voltage Packages 1.2 INT/3.3 EXT V 1.2 INT/3.3 EXT V 136-Lead BGA 136-Lead BGA pb free K indicates commercial grade temperature (0C to +70C). B indicates Ball Grid Array package. 3 Z indicates Lead Free package. For more information about lead free package offerings, please visit www.analog.com. Rev. PrA | Page 45 of 46 | December 2003 ADSP-21365 Preliminary Technical Data (c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. a Page 46 of 46 | December 2003 www.analog.com Rev. PrA | |
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